Crossbow - transition to Mercurial
1 /*
2 * Solaris driver for ethernet cards based on the ADMtek Centaur
3 *
4 * Copyright (c) 2007 by Garrett D'Amore <garrett@damore.org>.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the author nor the names of any co-contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS ``AS IS''
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31 /*
32 * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
33 * Use is subject to license terms.
34 */
35
36 #ifndef _AFEIMPL_H
37 #define _AFEIMPL_H
38
39 #pragma ident "%Z%%M% %I% %E% SMI"
40
41 #ifdef _KERNEL
42
43 /*
44 * Compile time tunables.
45 */
46 #define AFE_RXRING 128 /* number of rcv buffers */
47 #define AFE_TXRING 128 /* number of xmt buffers */
48 #define AFE_TXRECLAIM 8 /* when to reclaim tx buffers (txavail) */
49 #define AFE_TXRESCHED 120 /* when to resched (txavail) */
50 #define AFE_LINKTIMER 5000 /* how often we check link state (in msec) */
51 #define AFE_HEADROOM 34 /* headroom in packet (should be 2 modulo 4) */
52
53 /*
54 * Constants, do not change.
55 */
56 #define AFE_BUFSZ (1664) /* big enough for a vlan frame */
57 #define AFE_MCHASH (64)
58
59 typedef struct afe afe_t;
60 typedef struct afe_card afe_card_t;
61 typedef struct afe_rxbuf afe_rxbuf_t;
62 typedef struct afe_txbuf afe_txbuf_t;
63 typedef struct afe_desc afe_desc_t;
64
65 /*
66 * Card models.
67 */
68 typedef enum {
69 MODEL_CENTAUR = 1,
70 MODEL_COMET,
71 } afe_model_t;
72
73 struct afe_card {
74 uint16_t card_venid; /* PCI vendor id */
75 uint16_t card_devid; /* PCI device id */
76 char *card_cardname; /* Description of the card */
77 afe_model_t card_model; /* Card specific flags */
78 };
79
80 /*
81 * Device instance structure, one per PCI card.
82 */
83 struct afe {
84 dev_info_t *afe_dip;
85 mac_handle_t afe_mh;
86 afe_card_t *afe_cardp;
87 uint16_t afe_cachesize;
88 uint8_t afe_sromwidth;
89 int afe_flags;
90 kmutex_t afe_xmtlock;
91 kmutex_t afe_intrlock;
92 ddi_iblock_cookie_t afe_icookie;
93
94 /*
95 * Register and DMA access.
96 */
97 uintptr_t afe_regs;
98 ddi_acc_handle_t afe_regshandle;
99
100 /*
101 * Receive descriptors.
102 */
103 int afe_rxhead;
104 struct afe_desc *afe_rxdescp;
105 ddi_dma_handle_t afe_rxdesc_dmah;
106 ddi_acc_handle_t afe_rxdesc_acch;
107 uint32_t afe_rxdesc_paddr;
108 struct afe_rxbuf **afe_rxbufs;
109
110 /*
111 * Transmit descriptors.
112 */
113 int afe_txreclaim;
114 int afe_txsend;
115 int afe_txavail;
116 struct afe_desc *afe_txdescp;
117 ddi_dma_handle_t afe_txdesc_dmah;
118 ddi_acc_handle_t afe_txdesc_acch;
119 uint32_t afe_txdesc_paddr;
120 struct afe_txbuf **afe_txbufs;
121 hrtime_t afe_txstall_time;
122 boolean_t afe_wantw;
123
124 /*
125 * Link state.
126 */
127 uint64_t afe_lastifspeed;
128 link_state_t afe_linkup;
129 link_duplex_t afe_lastduplex;
130 link_duplex_t afe_duplex;
131 uint64_t afe_ifspeed;
132 boolean_t afe_resetting; /* no link warning */
133
134 /*
135 * Transceiver stuff.
136 */
137 int afe_phyaddr;
138 int afe_phyid;
139 int afe_phyinuse;
140
141 uint8_t afe_adv_aneg;
142 uint8_t afe_adv_100T4;
143 uint8_t afe_adv_100fdx;
144 uint8_t afe_adv_100hdx;
145 uint8_t afe_adv_10fdx;
146 uint8_t afe_adv_10hdx;
147 uint8_t afe_cap_aneg;
148 uint8_t afe_cap_100T4;
149 uint8_t afe_cap_100fdx;
150 uint8_t afe_cap_100hdx;
151 uint8_t afe_cap_10fdx;
152 uint8_t afe_cap_10hdx;
153
154 int afe_forcefiber;
155
156 /*
157 * Address management.
158 */
159 uchar_t afe_curraddr[ETHERADDRL];
160 boolean_t afe_promisc;
161 uint16_t afe_mccount[AFE_MCHASH];
162 uint32_t afe_mctab[AFE_MCHASH / 32]; /* Centaur */
163
164 /*
165 * Kstats.
166 */
167 kstat_t *afe_intrstat;
168 uint64_t afe_ipackets;
169 uint64_t afe_opackets;
170 uint64_t afe_rbytes;
171 uint64_t afe_obytes;
172 uint64_t afe_brdcstxmt;
173 uint64_t afe_multixmt;
174 uint64_t afe_brdcstrcv;
175 uint64_t afe_multircv;
176 unsigned afe_norcvbuf;
177 unsigned afe_errrcv;
178 unsigned afe_errxmt;
179 unsigned afe_missed;
180 unsigned afe_underflow;
181 unsigned afe_overflow;
182 unsigned afe_align_errors;
183 unsigned afe_fcs_errors;
184 unsigned afe_carrier_errors;
185 unsigned afe_collisions;
186 unsigned afe_ex_collisions;
187 unsigned afe_tx_late_collisions;
188 unsigned afe_defer_xmts;
189 unsigned afe_first_collisions;
190 unsigned afe_multi_collisions;
191 unsigned afe_sqe_errors;
192 unsigned afe_macxmt_errors;
193 unsigned afe_macrcv_errors;
194 unsigned afe_toolong_errors;
195 unsigned afe_runt;
196 unsigned afe_jabber;
197 };
198
199 struct afe_rxbuf {
200 caddr_t rxb_buf;
201 ddi_dma_handle_t rxb_dmah;
202 ddi_acc_handle_t rxb_acch;
203 uint32_t rxb_paddr;
204 };
205
206 struct afe_txbuf {
207 caddr_t txb_buf;
208 uint32_t txb_paddr;
209 ddi_dma_handle_t txb_dmah;
210 ddi_acc_handle_t txb_acch;
211 };
212
213 /*
214 * Descriptor. We use rings rather than chains.
215 */
216 struct afe_desc {
217 unsigned desc_status;
218 unsigned desc_control;
219 unsigned desc_buffer1;
220 unsigned desc_buffer2;
221 };
222
223 #define PUTTXDESC(afep, member, val) \
224 ddi_put32(afep->afe_txdesc_acch, &member, val)
225
226 #define PUTRXDESC(afep, member, val) \
227 ddi_put32(afep->afe_rxdesc_acch, &member, val)
228
229 #define GETTXDESC(afep, member) \
230 ddi_get32(afep->afe_txdesc_acch, &member)
231
232 #define GETRXDESC(afep, member) \
233 ddi_get32(afep->afe_rxdesc_acch, &member)
234
235 /*
236 * Receive descriptor fields.
237 */
238 #define RXSTAT_OWN 0x80000000U /* ownership */
239 #define RXSTAT_RXLEN 0x3FFF0000U /* frame length, incl. crc */
240 #define RXSTAT_RXERR 0x00008000U /* error summary */
241 #define RXSTAT_DESCERR 0x00004000U /* descriptor error */
242 #define RXSTAT_RXTYPE 0x00003000U /* data type */
243 #define RXSTAT_RUNT 0x00000800U /* runt frame */
244 #define RXSTAT_GROUP 0x00000400U /* multicast/brdcast frame */
245 #define RXSTAT_FIRST 0x00000200U /* first descriptor */
246 #define RXSTAT_LAST 0x00000100U /* last descriptor */
247 #define RXSTAT_TOOLONG 0x00000080U /* frame too long */
248 #define RXSTAT_COLLSEEN 0x00000040U /* late collision seen */
249 #define RXSTAT_FRTYPE 0x00000020U /* frame type */
250 #define RXSTAT_WATCHDOG 0x00000010U /* receive watchdog */
251 #define RXSTAT_DRIBBLE 0x00000004U /* dribbling bit */
252 #define RXSTAT_CRCERR 0x00000002U /* crc error */
253 #define RXSTAT_OFLOW 0x00000001U /* fifo overflow */
254 #define RXSTAT_ERRS (RXSTAT_DESCERR | RXSTAT_RUNT | \
255 RXSTAT_COLLSEEN | RXSTAT_DRIBBLE | \
256 RXSTAT_CRCERR | RXSTAT_OFLOW)
257 #define RXLENGTH(x) ((x & RXSTAT_RXLEN) >> 16)
258
259 #define RXCTL_ENDRING 0x02000000U /* end of ring */
260 #define RXCTL_CHAIN 0x01000000U /* chained descriptors */
261 #define RXCTL_BUFLEN2 0x003FF800U /* buffer 2 length */
262 #define RXCTL_BUFLEN1 0x000007FFU /* buffer 1 length */
263
264 /*
265 * Transmit descriptor fields.
266 */
267 #define TXSTAT_OWN 0x80000000U /* ownership */
268 #define TXSTAT_URCNT 0x00C00000U /* underrun count */
269 #define TXSTAT_TXERR 0x00008000U /* error summary */
270 #define TXSTAT_JABBER 0x00004000U /* jabber timeout */
271 #define TXSTAT_CARRLOST 0x00000800U /* lost carrier */
272 #define TXSTAT_NOCARR 0x00000400U /* no carrier */
273 #define TXSTAT_LATECOL 0x00000200U /* late collision */
274 #define TXSTAT_EXCOLL 0x00000100U /* excessive collisions */
275 #define TXSTAT_SQE 0x00000080U /* heartbeat failure */
276 #define TXSTAT_COLLCNT 0x00000078U /* collision count */
277 #define TXSTAT_UFLOW 0x00000002U /* underflow */
278 #define TXSTAT_DEFER 0x00000001U /* deferred */
279 #define TXCOLLCNT(x) ((x & TXSTAT_COLLCNT) >> 3)
280 #define TXUFLOWCNT(x) ((x & TXSTAT_URCNT) >> 22)
281
282 #define TXCTL_INTCMPLTE 0x80000000U /* interrupt completed */
283 #define TXCTL_LAST 0x40000000U /* last descriptor */
284 #define TXCTL_FIRST 0x20000000U /* first descriptor */
285 #define TXCTL_NOCRC 0x04000000U /* disable crc */
286 #define TXCTL_ENDRING 0x02000000U /* end of ring */
287 #define TXCTL_CHAIN 0x01000000U /* chained descriptors */
288 #define TXCTL_NOPAD 0x00800000U /* disable padding */
289 #define TXCTL_HASHPERF 0x00400000U /* hash perfect mode */
290 #define TXCTL_BUFLEN2 0x003FF800U /* buffer length 2 */
291 #define TXCTL_BUFLEN1 0x000007FFU /* buffer length 1 */
292
293
294 /*
295 * Interface flags.
296 */
297 #define AFE_RUNNING 0x1 /* chip is initialized */
298 #define AFE_SUSPENDED 0x2 /* interface is suspended */
299 #define AFE_HASFIBER 0x4 /* internal phy supports fiber (AFE_PHY_MCR) */
300
301 #define AFE_MODEL(afep) ((afep)->afe_cardp->card_model)
302
303
304 /*
305 * Register definitions located in afe.h exported header file.
306 */
307
308 /*
309 * Macros to simplify hardware access.
310 */
311 #define GETCSR(afep, reg) \
312 ddi_get32(afep->afe_regshandle, (uint32_t *)(afep->afe_regs + reg))
313
314 #define GETCSR16(afep, reg) \
315 ddi_get16(afep->afe_regshandle, (uint16_t *)(afep->afe_regs + reg))
316
317 #define PUTCSR(afep, reg, val) \
318 ddi_put32(afep->afe_regshandle, (uint32_t *)(afep->afe_regs + reg), val)
319
320 #define PUTCSR16(afep, reg, val) \
321 ddi_put16(afep->afe_regshandle, (uint16_t *)(afep->afe_regs + reg), val)
322
323 #define SETBIT(afep, reg, val) PUTCSR(afep, reg, GETCSR(afep, reg) | (val))
324
325 #define CLRBIT(afep, reg, val) PUTCSR(afep, reg, GETCSR(afep, reg) & ~(val))
326
327 #define SYNCTXDESC(afep, index, who) \
328 (void) ddi_dma_sync(afep->afe_txdesc_dmah, \
329 (index * sizeof (afe_desc_t)), sizeof (afe_desc_t), who)
330
331 #define SYNCTXBUF(txb, len, who) \
332 (void) ddi_dma_sync(txb->txb_dmah, 0, len, who)
333
334 #define SYNCRXDESC(afep, index, who) \
335 (void) ddi_dma_sync(afep->afe_rxdesc_dmah, \
336 (index * sizeof (afe_desc_t)), sizeof (afe_desc_t), who)
337
338 #define SYNCRXBUF(rxb, len, who) \
339 (void) ddi_dma_sync(rxb->rxb_dmah, 0, len, who)
340
341 /*
342 * Debugging flags.
343 */
344 #define DWARN 0x0001
345 #define DINTR 0x0002
346 #define DMACID 0x0008
347 #define DPHY 0x0020
348 #define DPCI 0x0040
349 #define DCHATTY 0x0080
350 #define DDMA 0x0100
351 #define DLINK 0x0200
352 #define DSROM 0x0400
353 #define DRECV 0x0800
354 #define DXMIT 0x1000
355
356 #ifdef DEBUG
357 #define DBG(lvl, ...) afe_dprintf(afep, __func__, lvl, __VA_ARGS__)
358 #else
359 #define DBG(lvl, ...)
360 #endif
361
362 #endif /* _KERNEL */
363
364 #endif /* _AFEIMPL_H */
--- EOF ---