Crossbow - transition to Mercurial
1 /* 2 * Solaris driver for ethernet cards based on the ADMtek Centaur 3 * 4 * Copyright (c) 2007 by Garrett D'Amore <garrett@damore.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the author nor the names of any co-contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS ``AS IS'' 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /* 32 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 33 * Use is subject to license terms. 34 */ 35 36 #ifndef _AFEIMPL_H 37 #define _AFEIMPL_H 38 39 #pragma ident "%Z%%M% %I% %E% SMI" 40 41 #ifdef _KERNEL 42 43 #include <sys/mac_provider.h> 44 45 /* 46 * Compile time tunables. 47 */ 48 #define AFE_RXRING 128 /* number of rcv buffers */ 49 #define AFE_TXRING 128 /* number of xmt buffers */ 50 #define AFE_TXRECLAIM 8 /* when to reclaim tx buffers (txavail) */ 51 #define AFE_TXRESCHED 120 /* when to resched (txavail) */ 52 #define AFE_LINKTIMER 5000 /* how often we check link state (in msec) */ 53 #define AFE_HEADROOM 34 /* headroom in packet (should be 2 modulo 4) */ 54 55 /* 56 * Constants, do not change. 57 */ 58 #define AFE_BUFSZ (1664) /* big enough for a vlan frame */ 59 #define AFE_MCHASH (64) 60 61 typedef struct afe afe_t; 62 typedef struct afe_card afe_card_t; 63 typedef struct afe_rxbuf afe_rxbuf_t; 64 typedef struct afe_txbuf afe_txbuf_t; 65 typedef struct afe_desc afe_desc_t; 66 67 /* 68 * Card models. 69 */ 70 typedef enum { 71 MODEL_CENTAUR = 1, 72 MODEL_COMET, 73 } afe_model_t; 74 75 struct afe_card { 76 uint16_t card_venid; /* PCI vendor id */ 77 uint16_t card_devid; /* PCI device id */ 78 char *card_cardname; /* Description of the card */ 79 afe_model_t card_model; /* Card specific flags */ 80 }; 81 82 /* 83 * Device instance structure, one per PCI card. 84 */ 85 struct afe { 86 dev_info_t *afe_dip; 87 mac_handle_t afe_mh; 88 afe_card_t *afe_cardp; 89 uint16_t afe_cachesize; 90 uint8_t afe_sromwidth; 91 int afe_flags; 92 kmutex_t afe_xmtlock; 93 kmutex_t afe_intrlock; 94 ddi_iblock_cookie_t afe_icookie; 95 96 /* 97 * Register and DMA access. 98 */ 99 uintptr_t afe_regs; 100 ddi_acc_handle_t afe_regshandle; 101 102 /* 103 * Receive descriptors. 104 */ 105 int afe_rxhead; 106 struct afe_desc *afe_rxdescp; 107 ddi_dma_handle_t afe_rxdesc_dmah; 108 ddi_acc_handle_t afe_rxdesc_acch; 109 uint32_t afe_rxdesc_paddr; 110 struct afe_rxbuf **afe_rxbufs; 111 112 /* 113 * Transmit descriptors. 114 */ 115 int afe_txreclaim; 116 int afe_txsend; 117 int afe_txavail; 118 struct afe_desc *afe_txdescp; 119 ddi_dma_handle_t afe_txdesc_dmah; 120 ddi_acc_handle_t afe_txdesc_acch; 121 uint32_t afe_txdesc_paddr; 122 struct afe_txbuf **afe_txbufs; 123 hrtime_t afe_txstall_time; 124 boolean_t afe_wantw; 125 126 /* 127 * Link state. 128 */ 129 uint64_t afe_lastifspeed; 130 link_state_t afe_linkup; 131 link_duplex_t afe_lastduplex; 132 link_duplex_t afe_duplex; 133 uint64_t afe_ifspeed; 134 boolean_t afe_resetting; /* no link warning */ 135 136 /* 137 * Transceiver stuff. 138 */ 139 int afe_phyaddr; 140 int afe_phyid; 141 int afe_phyinuse; 142 143 uint8_t afe_adv_aneg; 144 uint8_t afe_adv_100T4; 145 uint8_t afe_adv_100fdx; 146 uint8_t afe_adv_100hdx; 147 uint8_t afe_adv_10fdx; 148 uint8_t afe_adv_10hdx; 149 uint8_t afe_cap_aneg; 150 uint8_t afe_cap_100T4; 151 uint8_t afe_cap_100fdx; 152 uint8_t afe_cap_100hdx; 153 uint8_t afe_cap_10fdx; 154 uint8_t afe_cap_10hdx; 155 156 int afe_forcefiber; 157 158 /* 159 * Address management. 160 */ 161 uchar_t afe_curraddr[ETHERADDRL]; 162 boolean_t afe_promisc; 163 uint16_t afe_mccount[AFE_MCHASH]; 164 uint32_t afe_mctab[AFE_MCHASH / 32]; /* Centaur */ 165 166 /* 167 * Kstats. 168 */ 169 kstat_t *afe_intrstat; 170 uint64_t afe_ipackets; 171 uint64_t afe_opackets; 172 uint64_t afe_rbytes; 173 uint64_t afe_obytes; 174 uint64_t afe_brdcstxmt; 175 uint64_t afe_multixmt; 176 uint64_t afe_brdcstrcv; 177 uint64_t afe_multircv; 178 unsigned afe_norcvbuf; 179 unsigned afe_errrcv; 180 unsigned afe_errxmt; 181 unsigned afe_missed; 182 unsigned afe_underflow; 183 unsigned afe_overflow; 184 unsigned afe_align_errors; 185 unsigned afe_fcs_errors; 186 unsigned afe_carrier_errors; 187 unsigned afe_collisions; 188 unsigned afe_ex_collisions; 189 unsigned afe_tx_late_collisions; 190 unsigned afe_defer_xmts; 191 unsigned afe_first_collisions; 192 unsigned afe_multi_collisions; 193 unsigned afe_sqe_errors; 194 unsigned afe_macxmt_errors; 195 unsigned afe_macrcv_errors; 196 unsigned afe_toolong_errors; 197 unsigned afe_runt; 198 unsigned afe_jabber; 199 }; 200 201 struct afe_rxbuf { 202 caddr_t rxb_buf; 203 ddi_dma_handle_t rxb_dmah; 204 ddi_acc_handle_t rxb_acch; 205 uint32_t rxb_paddr; 206 }; 207 208 struct afe_txbuf { 209 caddr_t txb_buf; 210 uint32_t txb_paddr; 211 ddi_dma_handle_t txb_dmah; 212 ddi_acc_handle_t txb_acch; 213 }; 214 215 /* 216 * Descriptor. We use rings rather than chains. 217 */ 218 struct afe_desc { 219 unsigned desc_status; 220 unsigned desc_control; 221 unsigned desc_buffer1; 222 unsigned desc_buffer2; 223 }; 224 225 #define PUTTXDESC(afep, member, val) \ 226 ddi_put32(afep->afe_txdesc_acch, &member, val) 227 228 #define PUTRXDESC(afep, member, val) \ 229 ddi_put32(afep->afe_rxdesc_acch, &member, val) 230 231 #define GETTXDESC(afep, member) \ 232 ddi_get32(afep->afe_txdesc_acch, &member) 233 234 #define GETRXDESC(afep, member) \ 235 ddi_get32(afep->afe_rxdesc_acch, &member) 236 237 /* 238 * Receive descriptor fields. 239 */ 240 #define RXSTAT_OWN 0x80000000U /* ownership */ 241 #define RXSTAT_RXLEN 0x3FFF0000U /* frame length, incl. crc */ 242 #define RXSTAT_RXERR 0x00008000U /* error summary */ 243 #define RXSTAT_DESCERR 0x00004000U /* descriptor error */ 244 #define RXSTAT_RXTYPE 0x00003000U /* data type */ 245 #define RXSTAT_RUNT 0x00000800U /* runt frame */ 246 #define RXSTAT_GROUP 0x00000400U /* multicast/brdcast frame */ 247 #define RXSTAT_FIRST 0x00000200U /* first descriptor */ 248 #define RXSTAT_LAST 0x00000100U /* last descriptor */ 249 #define RXSTAT_TOOLONG 0x00000080U /* frame too long */ 250 #define RXSTAT_COLLSEEN 0x00000040U /* late collision seen */ 251 #define RXSTAT_FRTYPE 0x00000020U /* frame type */ 252 #define RXSTAT_WATCHDOG 0x00000010U /* receive watchdog */ 253 #define RXSTAT_DRIBBLE 0x00000004U /* dribbling bit */ 254 #define RXSTAT_CRCERR 0x00000002U /* crc error */ 255 #define RXSTAT_OFLOW 0x00000001U /* fifo overflow */ 256 #define RXSTAT_ERRS (RXSTAT_DESCERR | RXSTAT_RUNT | \ 257 RXSTAT_COLLSEEN | RXSTAT_DRIBBLE | \ 258 RXSTAT_CRCERR | RXSTAT_OFLOW) 259 #define RXLENGTH(x) ((x & RXSTAT_RXLEN) >> 16) 260 261 #define RXCTL_ENDRING 0x02000000U /* end of ring */ 262 #define RXCTL_CHAIN 0x01000000U /* chained descriptors */ 263 #define RXCTL_BUFLEN2 0x003FF800U /* buffer 2 length */ 264 #define RXCTL_BUFLEN1 0x000007FFU /* buffer 1 length */ 265 266 /* 267 * Transmit descriptor fields. 268 */ 269 #define TXSTAT_OWN 0x80000000U /* ownership */ 270 #define TXSTAT_URCNT 0x00C00000U /* underrun count */ 271 #define TXSTAT_TXERR 0x00008000U /* error summary */ 272 #define TXSTAT_JABBER 0x00004000U /* jabber timeout */ 273 #define TXSTAT_CARRLOST 0x00000800U /* lost carrier */ 274 #define TXSTAT_NOCARR 0x00000400U /* no carrier */ 275 #define TXSTAT_LATECOL 0x00000200U /* late collision */ 276 #define TXSTAT_EXCOLL 0x00000100U /* excessive collisions */ 277 #define TXSTAT_SQE 0x00000080U /* heartbeat failure */ 278 #define TXSTAT_COLLCNT 0x00000078U /* collision count */ 279 #define TXSTAT_UFLOW 0x00000002U /* underflow */ 280 #define TXSTAT_DEFER 0x00000001U /* deferred */ 281 #define TXCOLLCNT(x) ((x & TXSTAT_COLLCNT) >> 3) 282 #define TXUFLOWCNT(x) ((x & TXSTAT_URCNT) >> 22) 283 284 #define TXCTL_INTCMPLTE 0x80000000U /* interrupt completed */ 285 #define TXCTL_LAST 0x40000000U /* last descriptor */ 286 #define TXCTL_FIRST 0x20000000U /* first descriptor */ 287 #define TXCTL_NOCRC 0x04000000U /* disable crc */ 288 #define TXCTL_ENDRING 0x02000000U /* end of ring */ 289 #define TXCTL_CHAIN 0x01000000U /* chained descriptors */ 290 #define TXCTL_NOPAD 0x00800000U /* disable padding */ 291 #define TXCTL_HASHPERF 0x00400000U /* hash perfect mode */ 292 #define TXCTL_BUFLEN2 0x003FF800U /* buffer length 2 */ 293 #define TXCTL_BUFLEN1 0x000007FFU /* buffer length 1 */ 294 295 296 /* 297 * Interface flags. 298 */ 299 #define AFE_RUNNING 0x1 /* chip is initialized */ 300 #define AFE_SUSPENDED 0x2 /* interface is suspended */ 301 #define AFE_HASFIBER 0x4 /* internal phy supports fiber (AFE_PHY_MCR) */ 302 303 #define AFE_MODEL(afep) ((afep)->afe_cardp->card_model) 304 305 306 /* 307 * Register definitions located in afe.h exported header file. 308 */ 309 310 /* 311 * Macros to simplify hardware access. 312 */ 313 #define GETCSR(afep, reg) \ 314 ddi_get32(afep->afe_regshandle, (uint32_t *)(afep->afe_regs + reg)) 315 316 #define GETCSR16(afep, reg) \ 317 ddi_get16(afep->afe_regshandle, (uint16_t *)(afep->afe_regs + reg)) 318 319 #define PUTCSR(afep, reg, val) \ 320 ddi_put32(afep->afe_regshandle, (uint32_t *)(afep->afe_regs + reg), val) 321 322 #define PUTCSR16(afep, reg, val) \ 323 ddi_put16(afep->afe_regshandle, (uint16_t *)(afep->afe_regs + reg), val) 324 325 #define SETBIT(afep, reg, val) PUTCSR(afep, reg, GETCSR(afep, reg) | (val)) 326 327 #define CLRBIT(afep, reg, val) PUTCSR(afep, reg, GETCSR(afep, reg) & ~(val)) 328 329 #define SYNCTXDESC(afep, index, who) \ 330 (void) ddi_dma_sync(afep->afe_txdesc_dmah, \ 331 (index * sizeof (afe_desc_t)), sizeof (afe_desc_t), who) 332 333 #define SYNCTXBUF(txb, len, who) \ 334 (void) ddi_dma_sync(txb->txb_dmah, 0, len, who) 335 336 #define SYNCRXDESC(afep, index, who) \ 337 (void) ddi_dma_sync(afep->afe_rxdesc_dmah, \ 338 (index * sizeof (afe_desc_t)), sizeof (afe_desc_t), who) 339 340 #define SYNCRXBUF(rxb, len, who) \ 341 (void) ddi_dma_sync(rxb->rxb_dmah, 0, len, who) 342 343 /* 344 * Debugging flags. 345 */ 346 #define DWARN 0x0001 347 #define DINTR 0x0002 348 #define DMACID 0x0008 349 #define DPHY 0x0020 350 #define DPCI 0x0040 351 #define DCHATTY 0x0080 352 #define DDMA 0x0100 353 #define DLINK 0x0200 354 #define DSROM 0x0400 355 #define DRECV 0x0800 356 #define DXMIT 0x1000 357 358 #ifdef DEBUG 359 #define DBG(lvl, ...) afe_dprintf(afep, __func__, lvl, __VA_ARGS__) 360 #else 361 #define DBG(lvl, ...) 362 #endif 363 364 #endif /* _KERNEL */ 365 366 #endif /* _AFEIMPL_H */ --- EOF ---